The invention relates to a receiver device for receiving digital information in the form of electrical differential binary signals sent from a sender device. The receiver device through differential amplifier circuitry provides the information in a form suitable to digital logic circuits.
Advances in electronic technology and design, and a strive towards boosted performance in terms of power consumption and speed, among many other things, has led to a variety of concepts for digital logic circuits and digital signalling between circuits and circuit boards. Early concepts are DTL (Diode-Transistor Logic), TTL (Transistor-Transistor Logic) and ECL (Emitter Coupled Logic), which concepts are used both within digital logic circuits and for digital signalling between circuits and circuit boards.
More recent concepts, mostly used between circuits and circuit boards, employ differential signalling, also known as balanced signalling, which uses two signalling wires. DPECL (Differential Pseudo Emitter Coupled Logic), LVDS (Low Voltage Differential Signalling) and GLVDS (Grounded Low Voltage Differential Signalling) are examples of signalling concepts which use differential signalling. GLVDS is disclosed in the Swedish patent applications number SE 9304025-1 and number SE 9400971-9.
Although the above mentioned differential signalling concepts are indeed differential, each of the two signalling wires operate at fixed nominal voltages that are related to ground. Each wire operates at two voltage levels, referred to as low voltage level and high voltage level, respectively.
DPECL typically has a signalling low voltage level of 3.3 V, and a high level of 4.1 V. LVDS on the other hand has a low level of 1.0 V, and a high level of 1.4 V, while GLVDS has a low level of 0.1 V and a high level of 0.4 V. The voltages are related to ground. Signalling voltages hence span from almost 0 V up to more than 4 V.
A receiver device for receiving differential signals from the above described types of signalling concepts is often contained together with digital logic circuits in one integrated circuit, in order to reduce packaging, to reduce the required size of circuit-boards and, ultimately, to reduce cost. Preferably, a single supply-voltage is used for the integrated circuit, which supply voltage is shared both by the receiver device and by the digital logic circuits, whereby costly circuit technologies capable of handling multiple voltages are avoided. New circuit technologies however operate at very low supply voltages of 3.3 V or less, which enforces operation of the receiver device at these very low supply voltages.
At low supply voltages, only a small margin, if any, is provided for circuitry of a receiver device compatible with DPECL, LVDS, GLVDS and other signalling concepts. At a low supply voltage, circuitry of such a receiver device must operate at common-mode voltages both close to the supply voltage, or even above the supply voltage, and close to ground, preferably even lower than ground. Common-mode voltage refers to the average voltage, related to ground, at the inputs of circuitry known as a differential amplifier. Said receiver device is a differential amplifier. Differential amplifiers exist, which are capable of handling common-mode voltages close to the supply voltage, and close to ground. These are known as rail-to-rail amplifiers.
Known rail-to-rail amplifiers however exhibit a bandwidth and a propagation delay which are dependent on the applied common-mode voltage. This reduces the usable bandwidth and the ability of the amplifier to reject common-mode noise at high speeds, and makes signal skew quite unmanageable at high speeds.
Furthermore, known rail-to-rail amplifiers do not handle common-mode voltages higher than the supply voltage, or lower than ground. At a supply voltage of less than approximately 4.5 V, known rail-to-rail amplifiers are therefore not compatible with e.g. DPECL.
It is known in the art that a voltage dividing network is arranged at the inputs of a differential amplifier, for increasing the common-mode range. A voltage dividing network however attenuates the received signal, which makes it a poor solution for signals having low amplitudes. Moreover, process variations increase asymmetry of the received signal.
In U.S. Pat. No. 5,111,080 is disclosed a signal transmission circuit in which a signal is converted into two complementary signals which are output from a signal transmission circuit via series resistors. The amplitude of each of the complementary signals is reduced by the series resistors and terminating resistors provided on a signal receiving side. The signal receiving side shifts the level of its received input signal. The levelshifted signals are amplified by a high-input impedance differential amplifying circuit.
EP patent number 0579314A1 discloses an input buffer circuit. The input circuit receives a low level signal and a voltage reference, which are largely free from disturbing signals. The input buffer circuit comprises reducing means for reducing an offset voltage.
The Japanese patent number 4,767,979 discloses a switching circuit device which uses current mirror circuits. A first group of current mirror circuits is provided wherein a plurality of signal currents supplied via input terminals are superimposed upon mirror currents and signal currents resulting from the superimposition are derived as new mirror currents. A second group of current mirrors is provided to which the new mirror currents are supplied. The output stages of the second group of current mirror circuits are connected to each other at a common point which in turn is tied to the output stage of a current mirror circuit for supplying a mirror current of a predetermined magnitude. An output terminal is led out of said common point. Bias voltage for said second group of current mirror circuits is controlled so that any desired signal current is selected from said plurality of signal currents.
The Swedish patent application number 9400593-1 discloses a receiver device in which current mirrors are used in the input stage.